BUS_RESET_TYPE=Val_0x0
Reset Control Register
| SOFT_RST | Core Software Reset. This bit is cleared automatically once the core reset is complete. 1 (Val_0x1): To exercise core reset. This bit resets all buffers-receive, transmit, command, and response |
| CMD_QUEUE_RST | Command Queue Software Reset This bit is cleared automatically once the command queue reset is complete. 1 (Val_0x1): To exercise command queue reset |
| RESP_QUEUE_RST | Response Queue Software Reset This bit is cleared automatically once the response queue reset is complete. 1 (Val_0x1): To exercise response queue reset |
| TX_FIFO_RST | Transmit Buffer Software Reset This bit is cleared automatically once the Tx buffer reset is completed. 1 (Val_0x1): To exercise Tx buffer reset |
| RX_FIFO_RST | Receive Buffer Software Reset This bit is cleared automatically once the Rx buffer reset is completed. 1 (Val_0x1): To exercise Rx buffer reset |
| IBI_QUEUE_RST | IBI Queue Software Reset This bit is only used in Master mode of operation. This bit is cleared automatically once the IBI queue reset is completed. 1 (Val_0x1): To exercise IBI queue reset |
| BUS_RESET_TYPE | Bus Reset Type Type of bus reset triggered by BUS_RESET bit. Others: Reserved 0 (Val_0x0): Exit pattern 1 (Val_0x1): SCL low reset pattern |
| BUS_RESET | Bus Reset This bit is only used in Master mode of operation. This bit is cleared automatically once the bus reset pattern generation is completed. 1 (Val_0x1): To exercise bus reset pattern generation based on BUS_RESET_TYPE field. |